1. Field of the Invention
The present invention relates generally to data caches, and in particular to methods and mechanisms for reducing the number of clean victim writebacks from a data cache.
2. Description of the Related Art
Modern day mobile electronic devices often include multiple components or agents sharing access to one or more memory devices. These multiple agents may make large numbers of requests to memory, and as the number of these requests increases, the power consumption of the device increases, which limits the battery life of the device. One approach for reducing power consumption is to try to reduce the number of times that off-chip memory is accessed by caching data in or near the requesting agent.
Conventional caches are typically coupled to or nearby an agent and store data that is frequently accessed by the agent to reduce latency. For example, processor cores often include caches and may also be coupled to additional external caches in a cache memory hierarchy. In one embodiment, a system may include a processor, and the processor may include one or more level one (L1) caches, and the processor may be coupled to a level two (L2) cache. The system may also include a non-inclusive level three (L3) cache which is a victim cache for the write-back L2 cache. In such a system, capacity evictions from the L2 cache are sent to the L3 cache to be cached for future accesses. However, sending all capacity evictions diminishes the utility of the victim cache, increases the power consumed by the system, and decreases bandwidth availability for other agents.